Digital logic design using Verilog coding and RTL synthesis

Detalles Bibliográficos
Autor Principal:	Taraate, Vaibbhav (Author)
Autor Corporativo:	SpringerLink (Online service)
Formato:	Electronic Resource
Idioma:	English
Publicado:	New Delhi Springer India [2016]
Subjects:	Logic design > Data processing. Verilog (Computer hardware description language) Electronic books.
Acceso en liña:	Available for University of the Philippines System via SpringerLink. Click here to access Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy