Distributed sleep transistor network for power reduction.

Distributed sleep transistor network for power reduction.

Sleep transistors are effective to reduce leakage power during standby modes. The cluster-based design was proposed to save sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and inserting a sleep transistor per cluster. In this paper, we propose a n...

Full description

Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 9 (2004).
Main Author: Changbo Long
Format: Article
Language:English
Subjects:
Cluster-based design.
Clustering gates.
Gate level distributed sleep transistor network synthesis.
Leakage power.
Optimal designs.
Power reduction.
Switching current.