Design of FPGA interconnect for multilevel metallization.

How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring...

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發表在:	IEEE Transactions on VLSI systems 12, 10 (2004).
主要作者:	DeHon, A.
格式:	Article
語言:	英语
主題:	FPGA interconnection. FPGA place and route challenge. FPGA wiring schemes. Leighton mesh-of-trees. Manhattan FPGA routing scheme. Arbitrary device scaling. Arity-4 mesh-of-tree networks. Field programmable gate arrays. Metal layers. Multilevel metallization. Network size. Topology.