Design of FPGA interconnect for multilevel metallization.

Design of FPGA interconnect for multilevel metallization.

How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 10 (2004).
Main Author: DeHon, A.
Format: Article
Language:English
Subjects:
FPGA interconnection.
FPGA place and route challenge.
FPGA wiring schemes.
Leighton mesh-of-trees.
Manhattan FPGA routing scheme.
Arbitrary device scaling.
Arity-4 mesh-of-tree networks.
Field programmable gate arrays.
Metal layers.
Multilevel metallization.
Network size.
Topology.