A process-tolerant cache architecture for improved yield in nanoscale technologies.

A process-tolerant cache architecture for improved yield in nanoscale technologies.

Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 1 (2005).
Main Author: Agarwal, A.
Format: Article
Language:English
Subjects:
30 mV.
45 nm.
45-nm predictive technology.
50 nm.
64 K.
64-K direct map L1 cache.
SRAM cell failure mechanisms.
Cache resizing.
Contemporary fault tolerant method.
Error correcting code.
Failure mechanisms.
Faulty cell detection.
Faulty cell replacing.
High performance memory.
Minimum geometry transistors.
Nanoscale technologies.
Process parameter variations.
Process-tolerant cache architecture.
Row-column redundancy.
Sub-50-nm technology regime.