Efficient algorithms for multilevel power estimation of VLSI circuits.

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean powe...

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Publicado no:	IEEE Transactions on VLSI systems 13, 2 (2005).
Autor principal:	Bachmann, W.W
Formato:	Artigo
Idioma:	English
Assuntos:	ASIC library cells. CMOS technology. VLSI circuits. Benchmark circuits. Circuit models. Digital CMOS low-power design methods. Gate-level designs. Handling complex circuits. Integrated digital CMOS circuits. Mean power dissipation. Multilevel power estimation.