Efficient algorithms for multilevel power estimation of VLSI circuits.

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean powe...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 2 (2005).
第一著者:	Bachmann, W.W
フォーマット:	論文
言語:	English
主題:	ASIC library cells. CMOS technology. VLSI circuits. Benchmark circuits. Circuit models. Digital CMOS low-power design methods. Gate-level designs. Handling complex circuits. Integrated digital CMOS circuits. Mean power dissipation. Multilevel power estimation.