Efficient algorithms for multilevel power estimation of VLSI circuits.

Efficient algorithms for multilevel power estimation of VLSI circuits.

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean powe...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 13, 2 (2005).
Päätekijä: Bachmann, W.W
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
ASIC library cells.
CMOS technology.
VLSI circuits.
Benchmark circuits.
Circuit models.
Digital CMOS low-power design methods.
Gate-level designs.
Handling complex circuits.
Integrated digital CMOS circuits.
Mean power dissipation.
Multilevel power estimation.