A digit-serial multiplier for finite field GF(2m).

A digit-serial multiplier for finite field GF(2m).

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2m) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multipl...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 13, 4 (2005).
第一著者: Chang Hoon Kim
フォーマット: 論文
言語:English
主題:
VLSI implementation.
Computational delay time.
Dependence graph.
Digit-serial multiplier.
Finite field multiplication.
Least significant bit first multiplication algorithm.
Systolic array.
Unidirectional data flow.