A digit-serial multiplier for finite field GF(2m).

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2m) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multipl...

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Bibliographic Details

Published in:	IEEE Transactions on VLSI systems 13, 4 (2005).
Main Author:	Chang Hoon Kim
Format:	Article
Language:	English
Subjects:	VLSI implementation. Computational delay time. Dependence graph. Digit-serial multiplier. Finite field multiplication. Least significant bit first multiplication algorithm. Systolic array. Unidirectional data flow.