A 32-bit carry lookahead adder using dual-path all-N logic.

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race probl...

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Xuất bản năm:	IEEE Transactions on VLSI systems 13, 8 (2005).
Tác giả chính:	Ge Yang
Định dạng:	Bài viết
Ngôn ngữ:	English
Những chủ đề:	0.35 micron. 32 bit. ANT. CMOS chip. CMOS technology. DPANL adder. All-N transistor. Dual-path all-N logic. Dynamic logic circuit. Lookahead adder. Low power design. Post-layout simulation.