A 32-bit carry lookahead adder using dual-path all-N logic.

A 32-bit carry lookahead adder using dual-path all-N logic.

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race probl...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Τόπος έκδοσης:IEEE Transactions on VLSI systems 13, 8 (2005).
Κύριος συγγραφέας: Ge Yang
Μορφή: Άρθρο
Γλώσσα:English
Θέματα:
0.35 micron.
32 bit.
ANT.
CMOS chip.
CMOS technology.
DPANL adder.
All-N transistor.
Dual-path all-N logic.
Dynamic logic circuit.
Lookahead adder.
Low power design.
Post-layout simulation.