Formulating SoC test scheduling as a network transportation problem.

Formulating SoC test scheduling as a network transportation problem.

A formulation of core-based system-on-chip (SoC) test scheduling as a network transportation problem is presented. Given a set of tests, with demands for transportation of test bits (either for test stimuli or test response) and unrelated parallel test resources (e.g., test access mechanisms or buil...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on computer-aided design of integrated circuits and systems 21, 12 (2002).
1. autor: Koranne, S.
Format: Artykuł
Język:English
Hasła przedmiotowe:
NP-hard problem.
VLSI test.
Approximation algorithm.
Automatic test equipment.
Built-in self-test engines.
Computation time.
Core-based SoC test scheduling.
Demands for transportation.
Embedded core-based test scheduling.
Execution model.
Finish time minimization.
Network transportation problem.
Parallel test resources.
Parallel unrelated multiprocessor scheduling.
Resource mappings.
Schedule quality.
Single source unsplittable flow problem.
Start times.
Test access mechanisms.
Test response.
Test stimuli.