Formulating SoC test scheduling as a network transportation problem.

A formulation of core-based system-on-chip (SoC) test scheduling as a network transportation problem is presented. Given a set of tests, with demands for transportation of test bits (either for test stimuli or test response) and unrelated parallel test resources (e.g., test access mechanisms or buil...

詳細記述

書誌詳細
出版年:IEEE Transactions on computer-aided design of integrated circuits and systems 21, 12 (2002).
第一著者: Koranne, S.
フォーマット: 論文
言語:English
主題: