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Adding error-correcting circuitry to ASIC memory.

Thinking of putting ROM or RAM onto an application-specific IC? Then consider adding error-correction code (ECC) circuitry as well. Its presence boosts yield and reduces problems with random single-cell defects in memory arrays. Admittedly, the addition also expands chip area and impacts performance...

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Podrobná bibliografie
Vydáno v:IEEE spectrum 37, 4 (2000).
Hlavní autor: Gray, K.
Médium: Článek
Jazyk:angličtina
Témata:
ASIC memory.
XOR logic design.
Chip area.
Error-correcting circuitry.
Memory arrays.
Memory cell failure.
Performance.
Random single-cell defects.
Yield improvement.