A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.
The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit in...
| Εκδόθηκε σε: | IEEE Journal of solid state circuits 41, 4 (2006). |
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| Κύριος συγγραφέας: | |
| Μορφή: | Άρθρο |
| Γλώσσα: | Αγγλικά |
| Θέματα: |