A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.

The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit in...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 41, 4 (2006).
第一著者: Hwa-Joon Oh
フォーマット: 論文
言語:English
主題:
1.4 V.
128 bit.
16 bit.
32 bit.
56 C.
90 nm.
CELL processor.
SIMD unit.
Fine-grained clock gating.
Floating-point unit.
Microprocessor chips.
Single-instruction multiple-data unit.
Single-precision floating-point numbers.
Single-precision multiply-add operations.
Synergistic processor element.