Power optimized partial scan BIST implementation on DLX microprocessor
The need for efficient chip testing methods is needed as integrated circuits become more complex. Together with this is the increase in costs in terms of time and monetary resources with the use of external Automated Test Equipment (ATEs). One alternative is the incorporation of a Built-in Self-test...
| প্রধান লেখক: | |
|---|---|
| অন্যান্য লেখক: | , |
| বিন্যাস: | গবেষণাপত্র |
| ভাষা: | English |
| প্রকাশিত: |
2010
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| বিষয়গুলি: |