Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Dades bibliogràfiques
Autor principal: Taraate, Vaibbhav (Autor)
Autor corporatiu: SpringerLink (Online service)
Format: Electronic Resource
Idioma:English
Publicat: Singapore Springer [2019]
Edició:First edition.
Matèries:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Accés en línia:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy