Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Bibliografische gegevens
Hoofdauteur: Taraate, Vaibbhav (Auteur)
Coauteur: SpringerLink (Online service)
Formaat: Electronic Resource
Taal:English
Gepubliceerd in: Singapore Springer [2019]
Editie:First edition.
Onderwerpen:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Online toegang:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy