Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Bibliografski detalji
Glavni autor: Taraate, Vaibbhav (Autor)
Autor kompanije: SpringerLink (Online service)
Format: Electronic Resource
Jezik:English
Izdano: Singapore Springer [2019]
Izdanje:First edition.
Teme:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Online pristup:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy