Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Detalhes bibliográficos
Autor principal: Taraate, Vaibbhav (Author)
Autor Corporativo: SpringerLink (Online service)
Formato: Electronic Resource
Idioma:English
Publicado em: Singapore Springer [2019]
Edição:First edition.
Assuntos:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Acesso em linha:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy