Advanced HDL synthesis and SOC prototyping RTL design using verilog

Advanced HDL synthesis and SOC prototyping RTL design using verilog

Xehetasun bibliografikoak
Egile nagusia: Taraate, Vaibbhav (Egilea)
Erakunde egilea: SpringerLink (Online service)
Formatua: Electronic Resource
Hizkuntza:English
Argitaratua: Singapore Springer [2019]
Edizioa:First edition.
Gaiak:
Electronic circuits.
Logic design.
Microprogramming.
Electronic books.
Sarrera elektronikoa:Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy