APA (7th ed.) Zitazioa

Taraate, V. (2019). Advanced HDL synthesis and SOC prototyping: RTL design using verilog (First edition.). Springer. https://doi.org/10.1007/978-981-10-8776-9

Chicago Style (17th ed.) Zitazioa

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. First edition. Singapore: Springer, 2019. https://doi.org/10.1007/978-981-10-8776-9.

MLA (9th ed.) Zitazioa

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. First edition. Springer, 2019. https://doi.org/10.1007/978-981-10-8776-9.