Automatic analog IC sizing and optimization constrained with PVT corners and layout effects

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects

Xehetasun bibliografikoak
Egile Nagusiak: Lourenco, Nuno (Egilea), Martins, Ricardo (Egilea), Horta, Nuno C. G. (Egilea)
Erakunde egilea: SpringerLink (Online service)
Formatua: Electronic Resource
Hizkuntza:English
Argitaratua: Cham Springer [2017]
Gaiak:
Analog integrated circuits > Design.
Electronic books.
Sarrera elektronikoa:Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy