Cita APA (7th ed.)

Taraate, V. (2016). Digital logic design using Verilog: Coding and RTL synthesis. Springer India. https://doi.org/10.1007/978-81-322-2791-5

Cita Chicago (17th ed.)

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. New Delhi: Springer India, 2016. https://doi.org/10.1007/978-81-322-2791-5.

Cita MLA (9th ed.)

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. Springer India, 2016. https://doi.org/10.1007/978-81-322-2791-5.