PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process
| मुख्य लेखक: | |
|---|---|
| स्वरूप: | थीसिस |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
Quezon City
College of Engineering, University of the Philippines Diliman
2014.
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| विषय: |