PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process
| Autor principal: | |
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| Formato: | Thesis |
| Idioma: | inglês |
| Publicado em: |
Quezon City
College of Engineering, University of the Philippines Diliman
2014.
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| Assuntos: |