PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process
Challenges in designing the SmartWire node include voltage variation of 475mV to 500mV and temperature variation of 0° to 120°C on top of process variations while maintaining a maximum chip area of 5mm^2. However, because current digital design methodologies do not consider these challenges, failure...
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| Natura: | Tesi |
| Lingua: | English |
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Quezon City
College of Engineering, University of the Philippines Diliman
2014.
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