Low power networks-on-chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...

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Awdur Corfforaethol:	SpringerLink (Online service)
Awduron Eraill:	Silvano, Cristina, Lajolo, Marcello, Palermo, Gianluca
Fformat:	Electronic Resource
Iaith:	English
Cyhoeddwyd:	Boston Springer 2011.
Pynciau:	Electronic books. Networks on a chip.
Mynediad Ar-lein:	Available for University of the Philippines Diliman via SpringerLink.Click here to access