Low power networks-on-chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
| সংস্থা লেখক: | |
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| অন্যান্য লেখক: | , , |
| বিন্যাস: | Electronic Resource |
| ভাষা: | English |
| প্রকাশিত: |
Boston
Springer
2011.
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| বিষয়গুলি: | |
| অনলাইন ব্যবহার করুন: | Available for University of the Philippines Diliman via SpringerLink.Click here to access |