Low power networks-on-chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...

Täydet tiedot

Bibliografiset tiedot

Yhteisötekijä:	SpringerLink (Online service)
Muut tekijät:	Silvano, Cristina, Lajolo, Marcello, Palermo, Gianluca
Aineistotyyppi:	Electronic Resource
Kieli:	English
Julkaistu:	Boston Springer 2011.
Aiheet:	Electronic books. Networks on a chip.
Linkit:	Available for University of the Philippines Diliman via SpringerLink.Click here to access