Low power networks-on-chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
| 団体著者: | |
|---|---|
| その他の著者: | , , |
| フォーマット: | Electronic Resource |
| 言語: | English |
| 出版事項: |
Boston
Springer
2011.
|
| 主題: | |
| オンライン･アクセス: | Available for University of the Philippines Diliman via SpringerLink.Click here to access |