Low power networks-on-chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
| निगमित लेखक: | |
|---|---|
| अन्य लेखक: | , , |
| स्वरूप: | Electronic Resource |
| भाषा: | English |
| प्रकाशित: |
Boston
Springer
2011.
|
| विषय: | |
| ऑनलाइन पहुंच: | Available for University of the Philippines Diliman via SpringerLink.Click here to access |