Low power networks-on-chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...

Deskribapen osoa

Xehetasun bibliografikoak
Erakunde egilea: SpringerLink (Online service)
Beste egile batzuk: Silvano, Cristina, Lajolo, Marcello, Palermo, Gianluca
Formatua: Electronic Resource
Hizkuntza:English
Argitaratua: Boston Springer 2011.
Gaiak:
Sarrera elektronikoa:Available for University of the Philippines Diliman via SpringerLink.Click here to access