The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Библиографические подробности
Главный автор: Jespers, Paul G.
Формат: ‌
Язык:English
Опубликовано: New York Springer 2010.
Серии:Analog circuits and signal processing series.
Предметы:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.