The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Opis bibliograficzny
1. autor: Jespers, Paul G.
Format: Książka
Język:English
Wydane: New York Springer 2010.
Seria:Analog circuits and signal processing series.
Hasła przedmiotowe:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.