The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Detalles Bibliográficos
Autor Principal: Jespers, Paul G.
Formato: Libro
Idioma:English
Publicado: New York Springer 2010.
Series:Analog circuits and signal processing series.
Subjects:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.