The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Xehetasun bibliografikoak
Egile nagusia: Jespers, Paul G.
Formatua: Liburua
Hizkuntza:English
Argitaratua: New York Springer 2010.
Saila:Analog circuits and signal processing series.
Gaiak:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.