The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Jespers, Paul G.
Μορφή: Βιβλίο
Γλώσσα:English
Έκδοση: New York Springer 2010.
Σειρά:Analog circuits and signal processing series.
Θέματα:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.