The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

Bibliographische Detailangaben
1. Verfasser: Jespers, Paul G.
Format: Buch
Sprache:English
Veröffentlicht: New York Springer 2010.
Schriftenreihe:Analog circuits and signal processing series.
Schlagworte:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.