The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

গ্রন্থ-পঞ্জীর বিবরন
প্রধান লেখক: Jespers, Paul G.
বিন্যাস: গ্রন্থ
ভাষা:English
প্রকাশিত: New York Springer 2010.
মালা:Analog circuits and signal processing series.
বিষয়গুলি:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.