The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits the semi-empirical and compact model approaches

書誌詳細
第一著者: Jespers, Paul G.
フォーマット: 図書
言語:English
出版事項: New York Springer 2010.
シリーズ:Analog circuits and signal processing series.
主題:
Metal oxide semiconductors, Complementary > Design and construction.
Low voltage integrated circuits > Design and construction.
Linear integrated circuits > Design and construction.