Jespers, P. G. (2010). The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits: The semi-empirical and compact model approaches. Springer.
Lua i Stíl Chicago (17ú heag.)Jespers, Paul G. The Gm/ID Design Methodology, a Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. New York: Springer, 2010.
Lua MLA (9ú heag.)Jespers, Paul G. The Gm/ID Design Methodology, a Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. Springer, 2010.
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