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Random access at double the speed.

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Bibliografske podrobnosti
izdano v:IEEE spectrum 39, 8(duplicate) (2002).
Glavni avtor: Geppert, N.
Format: Article
Jezik:angleščina
Teme:
512 Kbit.
ASIC.
IBM demonstration chip.
Architectural device.
Circuit blocks.
Dynamic memory architecture.
Embedded DRAM.
Macros.
On-chip memory applications.
Systems-on-chip.
Write-back buffer.