A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we mod...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 11, 6 (2003).
第一著者: Azadpour, M.A
フォーマット: 論文
言語:English
主題:
RC model.
RLC.
Clock interconnect extractor.
Clock interconnect optimization.
Design optimization.
Electric design automation.
Inductance effect.
Interconnect inductance.
On-chip delay analysis.
On-chip interconnect.
Static-extraction analysis.