A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we mod...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 11, 6 (2003).
Päätekijä: Azadpour, M.A
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
RC model.
RLC.
Clock interconnect extractor.
Clock interconnect optimization.
Design optimization.
Electric design automation.
Inductance effect.
Interconnect inductance.
On-chip delay analysis.
On-chip interconnect.
Static-extraction analysis.