Fixed-outline floorplanning enabling hierarchical design.
Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant t...
| izdano v: | IEEE Transactions on VLSI systems 11, 6 (2003). |
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| Glavni avtor: | |
| Format: | Article |
| Jezik: | angleščina |
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