Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.
We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circui...
| الحاوية / القاعدة: | IEEE Transactions on VLSI systems 11, 6 (2003). |
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| المؤلف الرئيسي: | |
| التنسيق: | مقال |
| اللغة: | English |
| الموضوعات: |