Ultra-low-power DLMS adaptive filter for hearing aid applications.

Ultra-low-power DLMS adaptive filter for hearing aid applications.

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate th...

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Bibliografski detalji
Izdano u:IEEE Transactions on VLSI systems 11, 6 (2003).
Glavni autor: Kim, C.H.-I
Format: Članak
Jezik:English
Teme:
0.30 V.
0.35 micron.
0.67 V.
0.82 V.
21.4 nW.
22 kHz.
23.1 kHz.
400 mV.
Adaptive body biasing scheme.
Array multiplier test chip.
Delayed least mean square adaptive filter operation.
Hearing aid applications.
Lower clock rate.
Power-delay product.
pseudo nMOS logic style.
Robust operation.
Subpseudo nMOS.
Subthreshold CMOS logic.
Ultra-low-power DLMS adaptive filter.