Kansikuva

High-throughput LDPC decoders.

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding al...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 11, 6 (2003).
Päätekijä: Mansour, M.M
Aineistotyyppi: Artikkeli
Kieli:englanti
Aiheet:
288 byte.
Balh-Cocke-Jelinek-Raviv algorithm.
Dynamic transport network.
Interconnect complexity.
Interconnect length.
Low-density parity-check decoders.
Memory overhead.
Memory-efficient decoder.
Merged-schedule merge-passing algorithm.
Multiple check to-bit message.
Optimizations.
Power consumption.
Routing messages.
Scalable message-transport network.
Silicon.
Soft-input soft-output message update mechanism.
Storing.
Turbo decoding algorithm.