High-throughput LDPC decoders.

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding al...

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發表在:IEEE Transactions on VLSI systems 11, 6 (2003).
主要作者: Mansour, M.M
格式: Article
語言:English
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