Design of a 20-mb

The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data...

全面介紹

書目詳細資料

發表在:	IEEE Transactions on VLSI systems 11, 6 (2003).
主要作者:	Xun Liu
格式:	Article
語言:	英语
主題:	0.25 micron. 0.45 W. 20 Mbyte. RTL. Data transfer. Global buses. Global communication channels. High-throughput large-state Viterbi decoders. Interconnect effects. Interconnect wires. Parallel processors. Pipelined datapaths. Power dissipation. Register-transfer level implementation.