Timing driven gate duplication.

Timing driven gate duplication.

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary ou...

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Pubblicato in:IEEE Transactions on VLSI systems 12, 1 (2004).
Autore principale: Srivastava, A.
Natura: Articolo
Lingua:English
Soggetti:
Cutset minimization.
Delay constraints.
Delay optimization.
Dynamic programming structure.
Logic gates.
Logic synthesis.
Partitioning problems.
Primary inputs.
Primary outputs.
Timing driven gate duplication.
Topologically sorted order.
Tuple evaluation.
Ultra complex designs.